OISC CPU Operation

The OISC is built around a relatively simple architecture, an overview of which is given below.

Microcode State-Machine

The State Machine describes the heart of the CPU; the operations performed and the control lines enabled with each clock cycle. No operation pipelining was implemented.

The turquoise bootstrap function states perform the EEPROM to RAM copy on boot/reset, iterating until all the EEPROM has been fully copied (dictated by a solder jumper on the EEPROM module board).
State #2 allows the user to pause the CPU operation after the EEPROM copy, allowing the clock speed or mode to be changed before running the program.
The orange states implement the SUBLEQ instruction in 6 or 7 clock cycles, depending on the branch condition. The microcode below gives more details on the functionality of these states.
The purple state is envisaged for future operation, where an interrupt (potentially for drawing to a VGA screen) pauses the SUBLEQ operations (at the completion of a whole operation) and allows the routines on a VGA module to run uninterrupted until control is ceded back to the state machine.

The microcode describes each of the orange SUBLEQ states in more detail, including the control signals. The data transfer between memory and registers is also given for each state, including the program counter. Note that the RAM is considered an array called MEM[].

The truth table shown below describes the microcode logical outputs from the state machine (excluding next states). The outputs are used in conjunction with the EEPROM-based static logic to form all the required control signals used within the CPU and on the system bus.

Register and Memory Access

There are three 16-bit registers that each have tri-state connections to the two 16-bit buses.

An Arithmetic Logic Unit (ALU) performs the rudimentary logic associated with subtraction for the SUBLEQ instruction.
Program Counter (REG_PCNT) stores the current memory location of the running program. It is implemented with a programmable counter (it can either have a location loaded into it, or its value incremented by one).
Address Register (REG_ADDR) is used to store an address from the Data Bus and write it to the Address Bus.
Data Register (REG_DATA) stores data from the Data Bus (via the ALU as the data is transferred to the register) and writes it back to the Data Bus.

In addition to the Data Bus and Address Bus, there are a number of control signals - which together all form the system bus, interconnecting all the areas of the CPU and the external modules.

The memory timing diagram shows the data validity and clock timing for memory reading (the leftmost state) and memory writing (on the right), each taking a clock cycle (with a spare clock cycle between just for viewing clarity).

During the memory read cycle, data is nominally on the bus for the whole cycle, but latched into registers on the trailing clock edge (and into the low half of the clock cycle).
During the memory write cycle, data is nominally on the bus for the whole cycle, but latched into memory when the WE# signal rises, so it is stored at the start of the low half of the clock cycle.

CPU Schematic Design

The CPU schematic was designed using EasyEDA and routed with Freerouting. The resulting hexagonal 4-layer board and SMA were fabricated and produced by JLC PCB with surface-mount devices.

The implementation of the registers is partly shown in schematic form below.

The Address Register and Data Register were formed using multiple 8-bit D-Type flip-flop registers and Tri-State output drivers.
The Program Counter used 4 x 4-bit daisy-chained up/down programmable (loadable) counters. (Counting-down was disabled as it was never required.)

Part of the ALU implementation is shown below with daisy chained 4-bit adders. The lowest "carry in (C0)" is used to add a 1 to the inverted input, resulting in a 2's-complement negation. Ergo, the subtraction command (highly utilised in SUBLEQ) is neatly performed. Note the XOR ICs are used to perform logical input inversion of the data bus. The AND IC's are used as a select switch for the non-inverted input from the data register.